proc SCHEMATIC_bang_bang_cdr {} {
make constant -name xi0 -consval 0 -origin {30 30}
make name_net -name vin -origin {1050 70}
make edgemeasure -name xi15 -origin {1400 260}
make edgemeasure -name xi16 -origin {1400 380}
make output -name edge_ref -origin {1490 390}
make ch_pump -name xi2 -ival 150e-6 -origin {710 70}
make output -name clk_out -origin {1490 50}
make output -name edge_clk -origin {1490 270}
make output -name data_out -origin {1490 -60}
make signal_source -name xi1 -stype 3 -freq 2.502e9 -origin {200 50}
make bang_bang_detector -name xi4 -origin {500 40}
make vco_with_noise -name xi13 -fc 2.5e9 -kv 50e6 -foffset 1e6 -noise_at_foffset -90 -origin {1140 90}
make add2 -name xi6 -origin {990 70}
make name_net -name ph_err -origin {610 70}
make gain -name xi5 -gain 0.83e3 -origin {880 200}
make integrator -name xi3 -k 1/0.6e-9 -origin {880 70}
  make_wire 1210 50 1310 50
  make_wire 1050 70 1020 70
  make_wire 1050 70 1070 70
  make_wire 1310 270 1340 270
  make_wire 1460 390 1490 390
  make_wire 390 270 1310 270
  make_wire 1310 50 1490 50
  make_wire 1460 270 1490 270
  make_wire 360 390 1340 390
  make_wire 580 30 600 30
  make_wire 1490 -60 600 -60
  make_wire 100 30 70 30
  make_wire 360 110 360 390
  make_wire 330 30 420 30
  make_wire 390 70 390 270
  make_wire 600 -60 600 30
  make_wire 390 70 420 70
  make_wire 330 110 360 110
  make_wire 1310 50 1310 270
  make_wire 920 70 960 70
  make_wire 810 200 840 200
  make_wire 930 200 990 200
  make_wire 810 70 790 70
  make_wire 810 70 840 70
  make_wire 610 70 580 70
  make_wire 610 70 640 70
  make_wire 990 100 990 200
  make_wire 810 70 810 200
  make_text -origin {560 470} -text {To observe PLL dynamics at input to VCO:}
  make_text -origin {560 500} -text plotsig(x,'vin')
  make_text -origin {560 550} -text {To observe instantaneous jitter:}
  make_text -origin {560 580} -text {plot_pll_jitter(x,'edge_ref ',5e3,'edge_clk')}
  make_text -origin {530 440} -text {In CppSimView:}
}

