proc SCHEMATIC_linear_cdr {} {
make constant -name xi0 -consval 0 -origin {60 30}
make name_net -name vin -origin {1050 70}
make edgemeasure -name xi15 -origin {1400 230}
make edgemeasure -name xi16 -origin {1400 350}
make output -name edge_ref -origin {1490 360}
make hogge_detector -name xi4 -origin {530 40}
make leadlagfilter -name xi3 -fp 40e6 -fz 73e3 -gain 1/(2e-9) -origin {930 70}
make ch_pump -name xi2 -ival 150e-6 -origin {720 70}
make output -name clk_out -origin {1490 50}
make output -name edge_clk -origin {1490 240}
make output -name data_out -origin {1490 -60}
make signal_source -name xi1 -stype 3 -freq 2.502e9 -origin {230 50}
make vco_with_noise -name xi13 -fc 2.5e9 -kv 30e6 -foffset 1e6 -noise_at_foffset -100 -origin {1140 90}
  make_wire 1210 50 1310 50
  make_wire 1050 70 1020 70
  make_wire 1050 70 1070 70
  make_wire 1310 240 1340 240
  make_wire 1460 360 1490 360
  make_wire 420 240 1310 240
  make_wire 420 70 450 70
  make_wire 1310 50 1490 50
  make_wire 1460 240 1490 240
  make_wire 390 360 1340 360
  make_wire 360 110 390 110
  make_wire 420 70 420 240
  make_wire 610 30 630 30
  make_wire 630 -60 630 30
  make_wire 800 70 840 70
  make_wire 610 70 650 70
  make_wire 1490 -60 630 -60
  make_wire 390 110 390 360
  make_wire 1310 50 1310 240
  make_wire 360 30 450 30
  make_wire 100 30 130 30
  make_text -origin {560 440} -text {To observe PLL dynamics at input to VCO:}
  make_text -origin {560 470} -text plotsig(x,'vin')
  make_text -origin {560 520} -text {To observe instantaneous jitter:}
  make_text -origin {560 550} -text {plot_pll_jitter(x,'edge_ref ',30e3,'edge_clk')}
  make_text -origin {530 410} -text {In CppSimView:}
}

