CppSim leverages Verilator to simulated Verilog modules within a C++
framework. For the most part, Verilator does not require modification
for this task The one exception is that CppSim utilizes fst files to
store data in a format that GTKwave can read in, and the version of
Verilator utilized here only supports VCD files.  With a goal of
minimizing changes to Verilator, I achieved fst support by hijacking
the Verilator_VCD class such that Verilator thinks it is saving to VCD
but is instead saving to FST.  The only change required to Verilator
is to replace the verilated_vcd_c.h file with the 'hijacked' version
within the include directory of the Verilator distribution.  The
verilated_vcd_c.cpp file is also changed out, but this can be done
without changing the Verilator/include directory.

As for compiling Verilator, it proceeds as normal (without any
modification). Within a Msys shell window, simply type:
./configure
and then
make
within the Verilator source directory.
Note:  for Windows, after running ./configure and before running make
       add the flag -mwindows for the linker options 
       within src/Makefile_obj.  In particular:
       change:  LDFLAGS += -L${exec_prefix}/lib
       to:  LDFLAGS += -L${exec_prefix}/lib -mwindows

The verilated_vcd_c.h file is then replaced with the file
CppSimShared/CommonCode/verilated_fst_c.h (and rename verilated_fst_c.h to
verilated_vcd_c.h)

Here is a summary of modifications of Verilator for use with CppSim:

1)  Compile Verilator package without modification from the downloaded version
      Exception:  for Windows, add -mwindows flag to linker as described above
2)  Within Verilator/include, replace verilated_vcd_c.h with
    CppSimShared/CommonCode/verilated_fst_c.h (and change name to
    verilated_vcd_c.h)
3)  Within the files that call the routines and Classes in the
    new verilated_vcd_c.h file, compile with the file:
    CppSimShared/CommonCode/verilated_fst_c.cpp 
    (this is done automatically by CppSim)
