// To include other Verilog files within a specified directory:
// cpp_verilator_include_dir:

// To specify Verilator command line options:
// cpp_verilator_options:

// To run a specified shell command before Verilator is run on this module:
// cpp_verilator_pre_command:

// -> Note that the above statements must be preceeded with '//' as shown

`define IN_BITS 24 
`define OUT_BITS 8 

module second_order_sd(in, clk, resetb, out);

output [`OUT_BITS-1:0] out;
input [`IN_BITS-1:0] in;		//24
input  clk, resetb;

wire  [`OUT_BITS-1:0] out;
wire  [`IN_BITS-1:0] error, fb, residue;

assign error = in + fb;
assign out = error[`IN_BITS-1:`IN_BITS-`OUT_BITS];
assign residue = {`OUT_BITS'h0,error[`IN_BITS-`OUT_BITS-1:0]};
mod_h mod_h_inst(fb, residue, clk, resetb);

endmodule


module mod_h(out, in, clk, resetb);

output [`IN_BITS-1:0] out;
input [`IN_BITS-1:0] in;
input clk, resetb;

reg [`IN_BITS-1:0] in_reg, out_reg;

assign out = out_reg;

always @(posedge clk or negedge resetb) begin
  if(!resetb) begin
      out_reg <=  `IN_BITS'h0;
      in_reg <=  `IN_BITS'h0;
  end
  else begin 
      out_reg <=  2*in - in_reg ;
      in_reg <= in;
  end
end

endmodule

