proc SCHEMATIC_gmsk_pll_transmitter {} {
make signal_source -name xi6 -freq 100e6 -origin {-720 -60}
make divider_ideal -orient RX -name xi8 -origin {-420 230}
make constant -name xi9 -consval 9 -origin {-670 320}
make output -name iout -origin {620 -100}
make output -name qout -origin {620 -60}
make name_net_s -name ch_out -origin {20 -80}
make name_net_s -name div -origin {-500 200}
make constant -name xi7 -origin {-880 -80}
make name_net_s -name filt_out -origin {250 -80}
make name_net -name down -origin {-370 -40}
make name_net -name up -origin {-370 -80}
make name_net -name iup -origin {-110 -80}
make name_net -name idown -origin {-90 -40}
make sub2 -name xi12 -origin {-40 -80}
make mixer -orient RX -name xi4 -origin {180 270}
make add2 -orient RX -name xi5 -origin {100 200}
make gmsk_limitamp -orient RX -name xi10 -origin {-70 200}
make mixer -orient RX -name xi11 -origin {270 200}
make name_net -name isig -origin {100 330}
make name_net -name qsig -origin {240 410}
make gmsk_dig_iq_generator -name xi13 -mod_enable mod_enable -data_period 100e6/symbol_rate -origin {-290 390}
make name_net -name la_out -origin {-190 200}
make name_net_s -orient RX -name la_in -origin {30 200}
make first_order_lowpass -name xi3 -fp pll_bw*1.414 -gain pll_bw*4.442*9/(30e6*100e-6) -origin {130 -80}
make first_order_lowpass -name xi18 -fp 4*symbol_rate -origin {120 410}
make first_order_lowpass -name xi17 -fp 4*symbol_rate -origin {-60 330}
make tristate_pfd -name xi14 -origin {-450 -60}
make name_net -name vin -origin {550 -20}
make name_net -name vin_filt -origin {580 360}
make accum_and_dump -name xi22 -origin {450 370}
make name_net -name clk -origin {-540 -80}
make name_net -name clk -origin {330 390}
make tristate_ch_pump_with_noise -name xi0 -i_up 100e-6 -i_down 100e-6 -thermal_noise_up 0 -thermal_noise_down 0 -origin {-240 -80}
make vco_quadrature_with_1f_noise -name xi1 -fc 900.0e6 -kv 30.0e6 -foffset 20e6 -noise_at_foffset -165 -origin {420 -60}
  make_wire -840 -80 -820 -80
  make_wire -340 260 -370 260
  make_wire -370 -40 -340 -40
  make_wire -370 -80 -400 -80
  make_wire -370 -20 -400 -20
  make_wire -370 -80 -340 -80
  make_wire -140 -80 -110 -80
  make_wire -70 -80 -110 -80
  make_wire 130 200 230 200
  make_wire 580 200 310 200
  make_wire -170 330 -140 330
  make_wire -530 -20 -500 -20
  make_wire 40 410 -200 410
  make_wire -200 370 -170 370
  make_wire -500 200 -530 200
  make_wire -500 200 -470 200
  make_wire 30 200 70 200
  make_wire 100 270 140 270
  make_wire -370 200 -190 200
  make_wire -190 200 -130 200
  make_wire 210 -80 250 -80
  make_wire 250 -80 320 -80
  make_wire -90 -20 -40 -20
  make_wire -10 -80 20 -80
  make_wire 20 -80 50 -80
  make_wire 100 330 20 330
  make_wire 100 330 180 330
  make_wire 270 240 270 410
  make_wire 180 310 180 330
  make_wire 240 410 200 410
  make_wire 240 410 270 410
  make_wire -170 330 -170 370
  make_wire -10 200 30 200
  make_wire 600 270 220 270
  make_wire -530 -20 -530 200
  make_wire -540 -80 -500 -80
  make_wire 330 390 370 390
  make_wire 600 -100 600 270
  make_wire 350 110 350 360
  make_wire 580 -60 580 200
  make_wire 520 -60 580 -60
  make_wire 580 -60 620 -60
  make_wire 520 -100 600 -100
  make_wire 600 -100 620 -100
  make_wire 560 -20 560 110
  make_wire 350 110 560 110
  make_wire 100 230 100 270
  make_wire 530 360 580 360
  make_wire -550 370 -380 370
  make_wire -550 -80 -550 370
  make_wire -630 320 -340 320
  make_wire -340 260 -340 320
  make_wire -140 -40 -90 -40
  make_wire -90 -40 -90 -20
  make_wire -40 -50 -40 -20
  make_wire -370 -40 -370 -20
  make_wire -550 -80 -590 -80
  make_wire -550 -80 -540 -80
  make_wire 520 -20 550 -20
  make_wire 550 -20 560 -20
  make_wire 350 360 370 360
  make_text -origin {330 470} -text {Accumulate and dump circuit
prevents aliasing when storing 
downsampled version of vin for
spectrum plot} -size large
  make_text -origin {-750 -150} -text {100 MHz clock} -size large
  make_text -origin {-780 250} -text {Input Divide Value = 9} -size large
  make_text -origin {-370 570} -text {Note: data_period is referenced
to clock periods of clk input
and must be integer-valued}
}

proc ICON_gmsk_pll_transmitter args {




  icon_setup $args {{origin {0 0}} {orient R0} {name x} {symbol_rate 1e6} {mod_enable 1} {pll_bw 2e6}}
icon_term -type output -origin {80 -20} -name iout
icon_term -type output -origin {80 20} -name qout
icon_property -origin {-80 -50} -label {$name}
  icon_property -origin {-80 140} -type user -name name -default x
  icon_line -80 -40 -80 50 80 50 80 -40 -80 -40
icon_property -origin {40 -20} -label I_out
icon_property -origin {40 20} -label Q_out
icon_property -origin {0 40} -anchor center -label gmsk_pll_transmitter
  icon_property -origin {-80 160} -type user -name symbol_rate -default 1e6
icon_property -origin {-70 60} -label {symbol_rate=$symbol_rate sym/sec}
icon_property -origin {-70 100} -label {mod_enable=$mod_enable}
  icon_property -origin {-80 200} -type user -name mod_enable -default 1
icon_property -origin {-70 80} -label {pll_bw=$pll_bw}
  icon_property -origin {-80 180} -type user -name pll_bw -default 2e6




}

