/////////////////////////////////////////////////////////////
// CppSim Sim File: test.par
// Cell: test_ds_ord3_1bit
// Library: Delta_sigma_examples
/////////////////////////////////////////////////////////////

// Number of simulation time steps
num_sim_steps: 10.0e6

// Time step of simulator (in seconds)
Ts: 1/10e6

output: test trigger=-clk 
probe: out_dt  out_dt_filt  out_ct  out_ct_filt in
       xiadc_dt.x1  xiadc_dt.x2  xiadc_dt.x3
       xiadc_ct.x1  xiadc_ct.x2  xiadc_ct.x3

global_param: 
clk_freq_gl = 1.0e6
adc_bw_gl = 20e3

alter: 
