proc SCHEMATIC_ds_dt_ord3_mash_3bit_uint {} {
make name_net -name x1 -origin {500 270}
make name_net -name x2 -origin {970 270}
make name_net -name x3 -origin {1450 270}
make name_net -name clk -origin {1140 330}
make name_net -name clk -origin {660 330}
make name_net -name clk -origin {950 580}
make reg_int -orient RX -name xi6 -origin {840 560}
make add2_int -orient RXY -name xi8 -origin {540 470}
make reg_int -orient RX -name xi1 -origin {1320 560}
make name_net -name clk -origin {1430 580}
make add2_int -orient RXY -name xi4 -origin {1020 470}
make gain_int -orient RX -name xi5 -gain_int -1 -origin {1220 550}
make add2_int -orient RX -name xi7 -origin {1130 470}
make gain_int -orient RX -name xi10 -gain_int -1 -origin {740 550}
make add2_int -orient RX -name xi11 -origin {650 470}
make output -orient RX -name out -origin {-360 470}
make name_net -name out1 -origin {500 330}
make name_net -name out2 -origin {970 330}
make name_net -name out3 -origin {1450 330}
make accum_uint_no_delay -name xi0 -n wid_in -origin {330 300}
make accum_uint_no_delay -name xi2 -n wid_in -origin {800 300}
make accum_uint_no_delay -name xi3 -n wid_in -origin {1280 300}
make sat_limits_uint -name xi12 -n wid_in -origin {90 260}
make name_net -name clk -origin {400 500}
make reg_int -orient RX -name xi13 -origin {290 480}
make input -name in -origin {-360 270}
make input -name clk -origin {-360 370}
make sampler_w_delay -name xi9 -origin {-190 270}
make name_net -name in_sampled -origin {-50 270}
  make_wire 500 270 430 270
  make_wire 500 270 700 270
  make_wire 1450 270 1380 270
  make_wire 970 270 900 270
  make_wire 970 270 1180 270
  make_wire 1180 330 1140 330
  make_wire 700 330 660 330
  make_wire 1380 580 1430 580
  make_wire 1020 330 1020 440
  make_wire 930 550 900 550
  make_wire 900 580 950 580
  make_wire 540 330 540 440
  make_wire 680 470 930 470
  make_wire 1450 550 1380 550
  make_wire 1130 500 1130 550
  make_wire 1100 470 1050 470
  make_wire 990 470 930 470
  make_wire 650 500 650 550
  make_wire 650 550 690 550
  make_wire 570 470 620 470
  make_wire 1450 330 1380 330
  make_wire 1450 470 1160 470
  make_wire 1130 550 1170 550
  make_wire 1450 330 1450 470
  make_wire 1450 470 1450 550
  make_wire 930 470 930 550
  make_wire 500 330 430 330
  make_wire 500 330 540 330
  make_wire 970 330 900 330
  make_wire 970 330 1020 330
  make_wire 230 270 170 270
  make_wire 230 330 200 330
  make_wire 350 500 400 500
  make_wire 350 470 510 470
  make_wire 230 470 -360 470
  make_wire -310 310 -310 370
  make_wire -270 310 -310 310
  make_wire -310 370 200 370
  make_wire -270 270 -360 270
  make_wire -360 370 -310 370
  make_wire -50 270 -110 270
  make_wire -50 270 10 270
  make_wire 200 330 200 370
}

proc ICON_ds_dt_ord3_mash_3bit_uint args {

  icon_setup $args {{origin {0 0}} {orient R0} {name x} {wid_in 16}}
icon_term -type input -origin {-120 -30} -name in
icon_term -type input -origin {-120 50} -name clk
icon_term -type output -origin {120 -30} -name out
icon_property -origin {-110 -30} -label in
icon_property -origin {-110 50} -label clk
icon_property -origin {110 -30} -anchor e -label out
icon_property -origin {-110 -80} -label {$name}
icon_property -origin {-110 -60} -label ds_dt_ord3_mash_3bit_uint
  icon_line -120 -70 120 -70 120 70 -120 70 -120 -70
icon_property -origin {-110 80} -label {wid_in=$wid_in  (<= 30 bits)}
  icon_property -origin {-110 110} -type user -name name -default x
  icon_property -origin {-110 130} -type user -name wid_in -default 16
  icon_line -120 40 -110 50 -120 60
icon_property -origin {-110 10} -label (wid_in)
icon_property -origin {110 10} -anchor e -label (wid_out=3)
icon_property -origin {110 -10} -anchor e -label (signed)
icon_property -origin {-110 -10} -label (unsigned)

}

