proc SCHEMATIC_sd_synth_fast_electrical {} {
make output -name out -origin {1630 70}
make name_net -name div_val -origin {950 400}
make name_net -name sd_in -origin {640 400}
make name_net -name pfdout -origin {600 -20}
make name_net -name ref -origin {470 70}
make constant -name xi0 -origin {230 90}
make vco -name xi1 -freq 20e6 -kvco 1 -origin {380 90}
make xorpfd -name xi12 -origin {530 100}
make ch_pump -name xi2 -ival 1.5e-6 -origin {690 70}
make step_in -name xi10 -vend in_gl+delta_gl -vstart in_gl -tstep step_time_gl -origin {540 400}
make output -name noiseout -origin {1630 150}
make sd_modulator -name xi9 -order 3 -origin {800 420}
make add2 -orient RY -name xi4 -origin {830 70}
make vco_and_divider_with_1f_noise -name xi6 -fc 1.84e9 -kv 30e6 -foffset 10e6 -noise_at_foffset -146 -fcorner 1e3 -origin {1450 110}
make name_net -name vin -origin {1310 70}
make global -name gnd -origin {900 170}
make global -name gnd -origin {1070 170}
make global -name gnd -origin {1170 260}
make global -name gnd -origin {1270 260}
make vccs -name G0 -gain -1 -origin {980 90}
make resistor -name R0 -resistance 495k -origin {1170 120}
make capacitor -name C1 -capacitance 27.2p -origin {1170 210}
make capacitor -name C0 -capacitance 2.8p -origin {1270 170}
make gated_charge_pump_noise -name xi3 -thermal_noise_pos 0.6e-12 -thermal_noise_neg 1.5e-12 -origin {820 -40}
  make_wire 310 90 270 90
  make_wire 600 70 570 70
  make_wire 600 70 620 70
  make_wire 640 400 580 400
  make_wire 640 400 740 400
  make_wire 470 70 450 70
  make_wire 470 70 490 70
  make_wire 1370 110 1350 110
  make_wire 770 70 800 70
  make_wire 1610 70 1530 70
  make_wire 1610 70 1630 70
  make_wire 470 130 470 310
  make_wire 1530 150 1630 150
  make_wire 1350 110 1350 400
  make_wire 770 -20 600 -20
  make_wire 900 150 920 150
  make_wire 1070 150 1070 170
  make_wire 1170 70 1050 70
  make_wire 1050 150 1070 150
  make_wire 1270 70 1170 70
  make_wire 1270 210 1270 260
  make_wire 1270 70 1270 130
  make_wire 1270 70 1310 70
  make_wire 1170 250 1170 260
  make_wire 1170 160 1170 170
  make_wire 1170 70 1170 80
  make_wire 690 440 740 440
  make_wire 690 310 470 310
  make_wire 690 310 1610 310
  make_wire 1310 70 1370 70
  make_wire 470 130 490 130
  make_wire 860 400 950 400
  make_wire 950 400 1350 400
  make_wire 920 70 860 70
  make_wire 900 150 900 170
  make_wire 690 310 690 440
  make_wire 1610 70 1610 310
  make_wire 830 10 830 40
  make_wire 600 70 600 -20
  make_text -origin {930 470} -text {Examples in CppSimView:}
  make_text -origin {960 510} -text {To observe dynamics:  select test.tr0}
  make_text -origin {960 540} -text {plotsig(x,'sd_in;vin')}
  make_text -origin {960 590} -text {To observe phase noise: select test_noise.tr0}
  make_text -origin {960 620} -text plot_pll_phasenoise(x,10e3,30e6,'noiseout')
}

