proc SCHEMATIC_test_electrical_rc_filters {} {
make global -name gnd -origin {150 1740}
make vcvs -name E0 -origin {530 1670}
make constant -name xi1 -consval 0 -origin {-300 1650}
make resistor_with_cap -orient R270 -name R3 -par_cap 10p -origin {150 1650}
make global -name gnd -origin {720 1740}
make name_net -name out_distrc -origin {770 1650}
make rc_filter_element -name xi2 -origin {200 2010}
make rc_filter_first_order -name xi3 -origin {200 2640}
make signal_source -name xi0 -freq 10e6 -origin {-160 1670}
make rc_filter_element -name xi4 -origin {620 2010}
make global -name gnd -origin {80 2080}
make global -name gnd -origin {80 2700}
make global -name gnd -origin {500 2080}
make global -name gnd -origin {500 2700}
make name_net -name in -origin {40 1650}
make rc_filter_first_order -name xi5 -origin {620 2640}
make global -name gnd -origin {80 2460}
make global -name gnd -origin {500 2460}
make name_net -name out_two_first_ord_be_rc -origin {820 2640}
make name_net -name out_two_first_ord_trap_rc -origin {820 2400}
make name_net -name out_two_first_ord_cpp_rc -origin {820 2230}
make rcfilter -name xi8 -fo 1/(2*pi*1e3*10e-12) -origin {200 2230}
make rcfilter -name xi9 -fo 1/(2*pi*1e3*10e-12) -origin {630 2230}
make rc_filter_first_order -name xi6 -electrical_integration_damping_factor 0.0 -origin {200 2400}
make rc_filter_first_order -name xi7 -electrical_integration_damping_factor 0.0 -origin {620 2400}
make global -name gnd -origin {90 1920}
make name_net -name out_sec_ord_rc -origin {820 1820}
make name_net -name out_sec_ord_elem_rc -origin {820 2020}
make resistor -orient R90 -name R0 -origin {190 1820}
make capacitor -name C0 -capacitance 10p -origin {280 1860}
make resistor -orient R90 -name R1 -origin {580 1820}
make capacitor -name C1 -capacitance 10p -origin {670 1860}
make name_net -name n0 -origin {430 1820}
make name_net -name n1 -origin {430 2020}
make name_net -name n2 -origin {430 2640}
make name_net -name n3 -origin {430 2400}
make name_net -name n4 -origin {430 2230}
  make_wire 150 1680 150 1730
  make_wire 190 1650 470 1650
  make_wire 0 2020 100 2020
  make_wire 0 1650 -30 1650
  make_wire 80 2070 80 2080
  make_wire 80 2070 100 2070
  make_wire 80 2690 80 2700
  make_wire 80 2690 100 2690
  make_wire 500 2690 520 2690
  make_wire 720 2020 820 2020
  make_wire 720 2640 820 2640
  make_wire 600 1730 720 1730
  make_wire 720 1730 720 1740
  make_wire 40 1650 0 1650
  make_wire 40 1650 110 1650
  make_wire 430 2020 520 2020
  make_wire 430 2640 520 2640
  make_wire 0 2400 100 2400
  make_wire 80 2450 80 2460
  make_wire 80 2450 100 2450
  make_wire 500 2450 520 2450
  make_wire 720 2400 820 2400
  make_wire 430 2400 520 2400
  make_wire 300 2020 430 2020
  make_wire 300 2640 430 2640
  make_wire 300 2400 430 2400
  make_wire 500 2690 500 2700
  make_wire 500 2070 520 2070
  make_wire 500 2070 500 2080
  make_wire 150 1730 150 1740
  make_wire 470 1730 150 1730
  make_wire 0 2230 160 2230
  make_wire 670 2230 820 2230
  make_wire 430 2230 590 2230
  make_wire 240 2230 430 2230
  make_wire 770 1650 600 1650
  make_wire 500 2450 500 2460
  make_wire 230 1820 280 1820
  make_wire 620 1820 670 1820
  make_wire 670 1820 820 1820
  make_wire 90 1910 280 1910
  make_wire 280 1910 670 1910
  make_wire 150 1820 0 1820
  make_wire 430 1820 280 1820
  make_wire 430 1820 540 1820
  make_wire 0 1650 0 1820
  make_wire 0 1820 0 2020
  make_wire 90 1910 90 1920
  make_wire 280 1900 280 1910
  make_wire 670 1900 670 1910
  make_wire 0 2020 0 2230
  make_wire 0 2640 100 2640
  make_wire 0 2230 0 2400
  make_wire 0 2400 0 2640
  make_text -origin {100 1610} -text {Distributed RC element}
  make_text -origin {200 1950} -text {Second order RC filter using CppSim electrical_element  modules}
  make_text -origin {180 2570} -text {Two cascaded first order RC filters (Backward Euler integration - default)}
  make_text -origin {480 1610} -text {Voltage buffer}
  make_text -origin {210 2330} -text {Two cascaded first order RC filters (Trapezoidal integration)}
  make_text -origin {210 2180} -text {Two cascaded first order RC filters (CppSim C++ modules)}
  make_line 890 1780 950 1780 950 2080 890 2080
  make_line 890 2160 950 2160 950 2460 890 2460
}

