Index: usrp_stuff.cpp
===================================================================
--- usrp_stuff.cpp	(revision 494)
+++ usrp_stuff.cpp	(working copy)
@@ -37,6 +37,16 @@
 #include "fusb_stuff.h"
 #include <usb.h>
 
+static const int AUX_RXAGC = 1<<8;
+static const int POWER_UP = 1<<7; // enables power supply
+static const int RX_TXN = 1<<6; // Tx only:  T/R antenna switch
+static const int RX2_RX1N = 1<<6; // Rx only: antenna switch between Rx2 and Tx/Rx port
+static const int ENABLE = 1<<5; // enables mixer
+static const int AUX_SEN = 1<<4;
+static const int AUX_SCLK = 1<<3;
+static const int PLL_LOCK_DETECT = 1<<2;
+static const int AUX_SDO = 1<<1;
+static const int CLOCK_OUT = 1<<0;
 
 /////// from  usrp_bytesex.h ///////////////////
 
@@ -1128,25 +1138,9 @@
 
 void set_flex_io(usrp_standard_rx *urx, int which_slot, char *control_string)
 {
-int AUX_RXAGC, POWER_UP, RX_TXN, RX2_RX1N, ENABLE;
-int AUX_SEN, AUX_SCLK, PLL_LOCK_DETECT, AUX_SDO, CLOCK_OUT;
 int dbid_val;
 double min_gain, max_gain, gain;
 
-AUX_RXAGC = 1<<8; 
-POWER_UP = 1<<7; // enables power supply
-RX_TXN = 1<<6; // Tx only:  T/R antenna switch for Tx/Rx port
-RX2_RX1N = 1<<6; // Rx only:  antenna switch between Rx2 and Tx/Rx port
-ENABLE = 1<<5; // enables mixer
-AUX_SEN = 1<<4;
-AUX_SCLK = 1<<3;
-PLL_LOCK_DETECT = 1<<2;
-AUX_SDO = 1<<1;
-CLOCK_OUT = 1<<0;
-
-// Note:  POWER_UP and RX2_RX1N are asserted low
-
-
 dbid_val = urx->daughterboard_id(which_slot);
 
 if (dbid_val == USRP_DBID_FLEX_2400_RX)
@@ -3112,13 +3106,13 @@
   d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
 					   fusb_block_size, fusb_nblocks);
 
-  _write_fpga_reg(FR_ATR_CTL, 0);		// zero Tx side Auto Transmit/Receive regs
-  _write_fpga_reg(FR_ATR_MASK_0, 0);	
-  _write_fpga_reg(FR_ATR_TXVAL_0, 0);
-  _write_fpga_reg(FR_ATR_RXVAL_0, 0);
-  _write_fpga_reg(FR_ATR_MASK_2, 0);
-  _write_fpga_reg(FR_ATR_TXVAL_2, 0);
-  _write_fpga_reg(FR_ATR_RXVAL_2, 0);
+  _write_fpga_reg(FR_ATR_CTL, 1);
+  _write_fpga_reg(FR_ATR_MASK_0, RX_TXN | ENABLE);	
+  _write_fpga_reg(FR_ATR_TXVAL_0, ENABLE);
+  _write_fpga_reg(FR_ATR_RXVAL_0, RX_TXN);
+  _write_fpga_reg(FR_ATR_MASK_2, RX_TXN | ENABLE);
+  _write_fpga_reg(FR_ATR_TXVAL_2, ENABLE);
+  _write_fpga_reg(FR_ATR_RXVAL_2, RX_TXN);
 }
 
 
@@ -3139,7 +3133,7 @@
     printf( "usrp_basic_tx: failed to fini AD9862 TX regs\n");
   }
 
-  _write_fpga_reg(FR_ATR_CTL, 0);	// disable Auto T/R
+  _write_fpga_reg(FR_ATR_CTL, 1);
 }
 
 bool
Index: usrp_stuff_mex.cpp
===================================================================
--- usrp_stuff_mex.cpp	(revision 494)
+++ usrp_stuff_mex.cpp	(working copy)
@@ -38,6 +38,16 @@
 #include "fusb_stuff.h"
 #include <usb.h>
 
+static const int AUX_RXAGC = 1<<8;
+static const int POWER_UP = 1<<7; // enables power supply
+static const int RX_TXN = 1<<6; // Tx only:  T/R antenna switch
+static const int RX2_RX1N = 1<<6; // Rx only: antenna switch between Rx2 and Tx/Rx port
+static const int ENABLE = 1<<5; // enables mixer
+static const int AUX_SEN = 1<<4;
+static const int AUX_SCLK = 1<<3;
+static const int PLL_LOCK_DETECT = 1<<2;
+static const int AUX_SDO = 1<<1;
+static const int CLOCK_OUT = 1<<0;
 
 /////// from  usrp_bytesex.h ///////////////////
 
@@ -3113,13 +3123,13 @@
   d_ephandle = d_devhandle->make_ephandle (USRP_TX_ENDPOINT, false,
 					   fusb_block_size, fusb_nblocks);
 
-  _write_fpga_reg(FR_ATR_CTL, 0);		// zero Tx side Auto Transmit/Receive regs
-  _write_fpga_reg(FR_ATR_MASK_0, 0);	
-  _write_fpga_reg(FR_ATR_TXVAL_0, 0);
-  _write_fpga_reg(FR_ATR_RXVAL_0, 0);
-  _write_fpga_reg(FR_ATR_MASK_2, 0);
-  _write_fpga_reg(FR_ATR_TXVAL_2, 0);
-  _write_fpga_reg(FR_ATR_RXVAL_2, 0);
+  _write_fpga_reg(FR_ATR_CTL, 1);
+  _write_fpga_reg(FR_ATR_MASK_0, RX_TXN | ENABLE);	
+  _write_fpga_reg(FR_ATR_TXVAL_0, ENABLE);
+  _write_fpga_reg(FR_ATR_RXVAL_0, RX_TXN);
+  _write_fpga_reg(FR_ATR_MASK_2, RX_TXN | ENABLE);
+  _write_fpga_reg(FR_ATR_TXVAL_2, ENABLE);
+  _write_fpga_reg(FR_ATR_RXVAL_2, RX_TXN);
 }
 
 
@@ -3140,7 +3150,7 @@
     mexPrintf( "usrp_basic_tx: failed to fini AD9862 TX regs\n");
   }
 
-  _write_fpga_reg(FR_ATR_CTL, 0);	// disable Auto T/R
+  _write_fpga_reg(FR_ATR_CTL, 1);
 }
 
 bool
