proc SCHEMATIC_ds_dt_ord3_hk_mash_3bit_uint {} {
make input -name in -origin {-310 1050}
make input -name clk -origin {-310 1130}
make name_net -name x1 -origin {550 1050}
make name_net -name x2 -origin {1030 1050}
make name_net -name x3 -origin {1480 1050}
make name_net -name clk -origin {1150 1130}
make name_net -name clk -origin {670 1130}
make name_net -name clk -origin {960 1420}
make name_net -name clk -origin {1440 1420}
make output -orient RX -name out -origin {-310 1310}
make name_net -name out1 -origin {550 1130}
make name_net -name out2 -origin {1030 1130}
make name_net -name out3 -origin {1480 1130}
make hk_mash_ord1_stage_uint -name xi21 -wid_in wid_in -a a -origin {360 1080}
make reg_int -orient RX -name xi22 -origin {850 1400}
make add2_int -orient RXY -name xi23 -origin {550 1310}
make reg_int -orient RX -name xi24 -origin {1330 1400}
make add2_int -orient RXY -name xi25 -origin {1030 1310}
make gain_int -orient RX -name xi26 -gain_int -1 -origin {1230 1390}
make add2_int -orient RX -name xi27 -origin {1140 1310}
make gain_int -orient RX -name xi28 -gain_int -1 -origin {750 1390}
make add2_int -orient RX -name xi29 -origin {660 1310}
make sat_limits_uint -name xi30 -n wid_in -origin {110 1040}
make hk_mash_ord1_stage_uint -name xi31 -wid_in wid_in -a a -origin {830 1080}
make hk_mash_ord1_stage_uint -name xi32 -wid_in wid_in -a a -origin {1310 1080}
make reg_int -orient RX -name xi1 -origin {300 1320}
make name_net -name clk -origin {410 1340}
make sampler_w_delay -name xi0 -origin {-160 1050}
make name_net -name in_sampled -origin {-30 1050}
  make_wire 1190 1130 1150 1130
  make_wire 710 1130 670 1130
  make_wire 1390 1420 1440 1420
  make_wire 940 1390 910 1390
  make_wire 910 1420 960 1420
  make_wire 690 1310 940 1310
  make_wire 1480 1390 1390 1390
  make_wire 1140 1340 1140 1390
  make_wire 1110 1310 1060 1310
  make_wire 1000 1310 940 1310
  make_wire 660 1340 660 1390
  make_wire 660 1390 700 1390
  make_wire 580 1310 630 1310
  make_wire 1140 1390 1180 1390
  make_wire 940 1310 940 1390
  make_wire 240 1050 190 1050
  make_wire 550 1130 550 1280
  make_wire 550 1130 480 1130
  make_wire 550 1050 480 1050
  make_wire 550 1050 710 1050
  make_wire 1030 1130 950 1130
  make_wire 1030 1050 950 1050
  make_wire 1030 1050 1190 1050
  make_wire 1030 1130 1030 1280
  make_wire 1430 1050 1480 1050
  make_wire 1480 1130 1480 1310
  make_wire 1480 1130 1430 1130
  make_wire 1480 1310 1480 1390
  make_wire 1480 1310 1170 1310
  make_wire 360 1310 520 1310
  make_wire 240 1310 -310 1310
  make_wire 360 1340 410 1340
  make_wire -240 1090 -280 1090
  make_wire -280 1130 240 1130
  make_wire -280 1090 -280 1130
  make_wire -310 1130 -280 1130
  make_wire -310 1050 -240 1050
  make_wire -80 1050 -30 1050
  make_wire 30 1050 -30 1050
}

proc ICON_ds_dt_ord3_hk_mash_3bit_uint args {


  icon_setup $args {{origin {0 0}} {orient R0} {name x} {wid_in 16} {a 15}}
icon_term -type input -origin {-120 -30} -name in
icon_term -type input -origin {-120 50} -name clk
icon_term -type output -origin {120 -30} -name out
icon_property -origin {-110 -30} -label in
icon_property -origin {-110 50} -label clk
icon_property -origin {110 -30} -anchor e -label out
icon_property -origin {-110 -80} -label {$name}
icon_property -origin {-110 -60} -label ds_dt_ord3_hk_mash_3bit_uint
  icon_line -120 -70 120 -70 120 70 -120 70 -120 -70
icon_property -origin {-110 80} -label {wid_in=$wid_in  (<= 30 bits)}
  icon_property -origin {-110 130} -type user -name name -default x
  icon_property -origin {-110 150} -type user -name wid_in -default 16
  icon_line -120 40 -110 50 -120 60
icon_property -origin {-110 10} -label (wid_in)
icon_property -origin {110 10} -anchor e -label (wid_out=3)
icon_property -origin {110 -10} -anchor e -label (signed)
icon_property -origin {-110 -10} -label (unsigned)
icon_property -origin {-110 100} -label {a=$a  (integer >= 0)}
  icon_property -origin {-110 170} -type user -name a -default 15


}

