/////////////////////////////////////////////////////////////
// CppSim Sim File: test.par
// Cell: test_ds_ct_ord2_candy_mbit
// Library: Delta_sigma_examples
/////////////////////////////////////////////////////////////

// Number of simulation time steps
num_sim_steps: 10e6

// Time step of simulator (in seconds)
Ts: 1/10e6

output: test trigger=-clk 
probe: out_4bit out_int_4bit out_4bit_filt
       out_2bit out_int_2bit out_2bit_filt
       xiadc_4bit.x1 xiadc_4bit.x2 
       xiadc_2bit.x1 xiadc_2bit.x2  in

global_param: 
clk_freq_gl = 1e6
adc_bw_gl = 20e3

alter: 
