module: example_five_bit_sar_algorithm
description: 
parameters:  
timing_sensitivity: posedge clk
inputs:  bool comp_result, bool clk
outputs:  bool sel_gnd[4:0], bool sel_ref_in[4:0], 
          bool sel_in, bool sel_ref, bool out
classes:  
static_variables: int internal_state, int counter
init:  

sel_gnd.set_decimal_value(0);
sel_ref_in.set_decimal_value(31);
sel_in = 1;
sel_ref = 0;
internal_state = 0;
out = 0;

code:  

/// the code here only executes on positive edges of the input clk
/// as specified by the 'timing_sensitivity:' statement above

if (internal_state == 0)
  {
   internal_state = 1;
   sel_in = 1;
   sel_ref = 0;
   counter = 4;
   sel_gnd.set_decimal_value(0);
   sel_ref_in.set_decimal_value(31);
  }
else if (internal_state == 1)
  {
   internal_state = 2;
   sel_in = 0;
   sel_ref = 1;
   sel_gnd.set_decimal_value(31);
   sel_ref_in.set_decimal_value(0);
  }
else
  {
   if (counter < 4)
     {
      if (comp_result == 1)
        {
         sel_gnd.set_elem(counter+1,1);
         sel_ref_in.set_elem(counter+1,0);
        }
     }
   if (counter >= 0)
     {
      sel_gnd.set_elem(counter,0);
      sel_ref_in.set_elem(counter,1);
     }
   else
     {
      internal_state = 0;
      out = sel_ref_in.get_decimal_value();
     }
   counter--;
  }

