proc SCHEMATIC_test_electrical_current_dac {} {
make global -orient RY -name vdd -origin {620 1030}
make global -name gnd -origin {620 1310}
make global -name gnd -origin {430 1310}
make name_net -name vdac_out -origin {670 1200}
make resistor -name R0 -origin {620 1100}
make constant -name xi5 -consval 0.0 -origin {-800 1050}
make signal_source -name xi7 -stype 1 -freq 10e3 -origin {-660 1070}
make constant -name xi1 -consval 0.0 -origin {-840 1390}
make signal_source -name xi2 -freq 1e6 -origin {-700 1410}
make name_net -name clk -origin {-530 1390}
make name_net -name in -origin {-370 1200}
make inv -name xi4 -origin {-440 1230}
make global -name gnd -origin {750 1310}
make capacitor -name C0 -capacitance 100p -origin {750 1260}
make name_net -name out<29:0> -origin {-80 1200}
make name_net -name vdac_in -origin {410 1200}
make vccs -name G0 -gain 1e-3 -origin {510 1220}
make dac_bits2double -name xi6 -origin {80 1210}
make quantizer_clocked_basic -name xi0 -origin {-240 1210}
make reg_double -name xi3 -origin {300 1210}
  make_wire 620 1030 620 1060
  make_wire -530 1050 -410 1050
  make_wire -530 1390 -570 1390
  make_wire -140 1200 -80 1200
  make_wire -370 1200 -410 1200
  make_wire -370 1200 -340 1200
  make_wire -410 1050 -410 1200
  make_wire -380 1230 -340 1230
  make_wire -470 1230 -500 1230
  make_wire -500 1390 -530 1390
  make_wire 750 1300 750 1310
  make_wire 450 1280 430 1280
  make_wire 430 1280 430 1310
  make_wire 580 1280 620 1280
  make_wire 620 1280 620 1310
  make_wire 620 1140 620 1200
  make_wire 620 1200 580 1200
  make_wire 620 1200 670 1200
  make_wire 670 1200 750 1200
  make_wire 750 1200 750 1220
  make_wire 410 1200 360 1200
  make_wire 410 1200 450 1200
  make_wire 210 1230 240 1230
  make_wire -500 1230 -500 1390
  make_wire 180 1200 240 1200
  make_wire -20 1200 -80 1200
  make_wire -20 1230 -50 1230
  make_wire -50 1230 -50 1390
  make_wire -50 1390 210 1390
  make_wire -50 1390 -500 1390
  make_wire 210 1230 210 1390
}

