module: reg_double_w_rst
description: 
timing_sensitivity: posedge clk or negedge rstb
parameters:  
inputs:  double in, bool clk
             bool rstb
outputs:  double out
classes:  
static_variables:  
init:  


end:  
code:  
if (rstb == 0)
   out = 0.0;
else
   out = in;