proc SCHEMATIC_spice_example1 {} {
make nmos -name M0 -origin {40 120}
make pmos -name M1 -origin {40 -50}
make input -name in -origin {-260 30}
make output -name out -origin {450 30}
make global -orient RXY -name vdd -origin {40 -110}
make global -name gnd -origin {40 180}
make global -name gnd -origin {240 180}
make resistor -orient R90 -name R2 -resistance 10k -origin {150 30}
make name_net -name n1 -origin {90 30}
make name_net -name n0 -origin {-130 30}
make resistor -orient R90 -name R0 -resistance 100k -origin {-30 40}
make resistor -orient R90 -name R1 -resistance 50k -origin {-200 30}
make capacitor -name C0 -capacitance 2p -origin {240 110}
make inverter -name xi0 -origin {340 30}
make name_net -name n2 -origin {260 30}
make global -name gnd -origin {420 180}
make capacitor -name C1 -capacitance 2p -origin {420 110}
  make_wire -20 -50 -100 -50
  make_wire -100 120 -20 120
  make_wire 40 -110 40 -90
  make_wire 40 160 40 180
  make_wire -70 40 -100 40
  make_wire 10 40 40 40
  make_wire -240 30 -260 30
  make_wire 240 30 190 30
  make_wire 90 30 40 30
  make_wire 90 30 110 30
  make_wire -160 30 -130 30
  make_wire -130 30 -100 30
  make_wire 260 30 310 30
  make_wire 260 30 240 30
  make_wire 420 30 390 30
  make_wire 420 30 450 30
  make_wire -100 40 -100 120
  make_wire 40 40 40 80
  make_wire 240 150 240 180
  make_wire 420 150 420 180
  make_wire 420 30 420 70
  make_wire -100 -50 -100 30
  make_wire -100 30 -100 40
  make_wire 40 -10 40 30
  make_wire 40 30 40 40
  make_wire 240 30 240 70
}

