/////////////////////////////////////////////////////////////
// CppSim Sim File: test.par
// Cell: test_ds_dt_ord2_candy_mbit_ver
// Library: Delta_sigma_examples
/////////////////////////////////////////////////////////////

// Number of simulation time steps
num_sim_steps: 10e6

// Time step of simulator (in seconds)
Ts: 1/10e6

output: test trigger=-clk start_time=1e-3
probe: out_1bit out_5bit out_1bit_filt out_5bit_filt in
       out_1bit_rfilt  out_5bit_rfilt

// output: test_gtk filetype=gtkwave trigger=-clk start_time=1e-3
// probe: xiadc1.*.*.*.*  xiadc5.*.*.*.*

global_param: 
clk_freq_gl = 1e6
adc_bw_gl = 20e3

alter: 
