proc SCHEMATIC_spice_example7 {} {
make global -name gnd -origin {800 510}
make dc_voltage -name Vin -ac_voltage 1 -origin {800 440}
make global -name gnd -origin {1110 510}
make capacitor -orient RXY -name C0 -capacitance 10p -origin {1110 430}
make capacitor -orient R270 -name C1 -capacitance 10p -origin {1250 330}
make global -name gnd -origin {1430 510}
make global -name gnd -origin {1740 510}
make global -name gnd -origin {2010 510}
make capacitor -orient RXY -name C2 -capacitance 10p -origin {1430 430}
make capacitor -orient RXY -name C3 -capacitance 10p -origin {1740 430}
make name_net -name out -origin {1990 330}
make resistor -orient R90 -name R0 -resistance r1_val -noise_enable r1_en -origin {950 330}
make resistor -orient R270 -name R1 -resistance r2_val -noise_enable r2_en -origin {1590 330}
make resistor -orient RX -name R2 -resistance r3_val -noise_enable r3_en -origin {2010 430}
  make_wire 800 480 800 510
  make_wire 800 330 910 330
  make_wire 800 330 800 400
  make_wire 990 330 1110 330
  make_wire 1110 470 1110 510
  make_wire 1110 330 1210 330
  make_wire 1110 330 1110 390
  make_wire 1430 470 1430 510
  make_wire 1290 330 1430 330
  make_wire 1430 330 1550 330
  make_wire 1430 330 1430 390
  make_wire 1740 470 1740 510
  make_wire 1740 330 1740 390
  make_wire 1630 330 1740 330
  make_wire 2010 470 2010 510
  make_wire 2010 330 2010 390
  make_wire 1990 330 1740 330
  make_wire 1990 330 2010 330
  make_text -origin {760 210} -text {In Python, run sim_noise.py in SimRuns/Spice/spice_example7 to see example of plotting spectrum of each noise source and overall total} -size large
}

