module: dco_phase_counter
sim_order:  xi0 xi1 xi2

module: counter_with_reset
parameters:
inputs:  double_interp clk double_interp reset
outputs:  int count
classes: EdgeDetect edge_clk(), EdgeDetect edge_reset();
static_variables:
init: count=0;
code:
if (edge_clk.inp(clk))
    count++;

if (edge_reset.inp(reset))
    count=0;

